Lab Report 8 (1)



Texas A&M University *

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Electrical Engineering


Dec 6, 2023





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ECEN 248 - Lab Report Lab 8 Counters, Clock Dividers, and Debounce Circuits Section 513 Zachary Rich 931009001 November 1, 2023 Ali Shawartamimi
Objectives: For this lab, I will be reinforcing my knowledge on sequential logic circuits by being introduced to the binary counter. I will be implementing the binary up-counter using components that I am familiar with. This will help me learn the 2 important use cases for binary counters. Design: For this lab, I started by starting the computer at my station and booted up Verilog. After it was ready, I started a new project, naming it “Lab_8”, and selected the correct board for the project. I then implemented the clock divider using code in Canvas. I then set up the FPGA board the way Canvas instructed me to do, including hooking it up to the Oscilloscope and the computer. After the board was properly programmed, I then ran the logic analyzer and took pictures of the data I then created and coded a half adder, and then coded the up-counter that was in Canvas, making sure to fill in what was missing. When I saw that I had successfully implemented it, I got the test bench file and ran the simulation, making sure to change the waveform settings to output what I needed. After that, I changed the count signal to 26 bits in the clock divider file and then created two top level files using the code from Canvas (one was a .v and the other was .xdc). I made sure to fill in everything missing from the files and then synthesized them. I then added the bounce test bench file, as well as the no debounce file, from Canvas, and ran them through a simulation. Results: For this lab, we did not get the end of part 2 done because we were one of the groups that none of us could figure out what was wrong with the code, so you gave us the pass and told us just to move on. Questions: 2.2b) What is the frequency of the signal? 20ns => 1/20 = 50MHz 2.2c) How long is that interval? 20ns 2.2d) How long is this time period? 30ns 2.2f) What is this maximum count value and what signal in the waveform could we use to know exactly when the counter is going to roll over? 7 & Carry2 2.3a) If we use a 125MHz clock to drive our frequency divider, what rate will the most significant bit of the divider oscillate at? (125*10 6 )/(2 26 ) = 1.862Hz
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