HW4

1. Develop a mathematical model for measuring performance based on overall memory access time with a neat diagram for the following memory design and derive the formula to calculate the Overall Memory Access Time. Main Memory : 1 Internal Cache : 1 External Cache: 1 Register S and Register B have fastest access time: Data Search order [ Registers – Internal Cache – External Cache – Memory] [Hint: Register access time is considered negligible]

4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:   Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit?    No hand written and fast answer with explanation

Suppose that a 32M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. (Please show detailed work) f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#") g) Repeat (f) for low-order interleaving.

In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code: sw r16,12(r6)lw r16,8(r6)beq r5,r4,Label # Assume r5!=r4add r5,r1,r4slt r5,r15,r4 Assume that individual pipeline stages have the following latencies: IF          ID        EX       MEM      WB200ps  120ps   150ps   190ps    100ps 1.1, For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that only…

4.18 [5] <COD §4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from COD Section 4.5 (An overview of pipelining) that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? ADDI X1, X2, #5   ADD X3, X1, X2   ADDI X4, X1, #15

Section 5.5 states that modern server memory modules (DIMMs) employ SEC/DED ECC to protect each 64 bits with 8 parity bits. Compute the cost/ performance ratio of this code to the code from 5.9.1. In this case, cost is the relative number of parity bits needed while performance is the relative number of errors that can be corrected. Which is better?

In this exercise, we examine how resource hazards, control hazards, and Instruction Set Architecture (ISA) design can affect pipelined execution. Problems in this exercise refer to the following fragment of MIPS code:   sw r16,12(r6) lw r16,8(r6) beq r5,r4,Label # Assume r5!=r4 add r5,r1,r4 Assume that individual pipeline stages have the following latencies:   IF            ID            EX           MEM     WB 200ps    120ps    150ps    190ps    100ps a. For this problem, assume that all branches are perfectly predicted (this eliminates all control hazards) and that no delay slots are used. If we only have one memory (for both instructions and data), there is a structural hazard every time we need to fetch an instruction in the same cycle in which another instruction accesses data. To guarantee forward progress, this hazard must always be resolved in favor of the instruction that accesses data. What is the total execution time of this instruction sequence in the 5-stage pipeline that…

1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines:   Program Time on M1 Time on M2 1 10 seconds 5 seconds 2 3 seconds 4 seconds Which machine is faster for each program, and by how much?   2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1.   Program Instructions executed on M1 Instructions executed on M2 1 200 x 106 160 x 106   3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2.   4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…

1,  Explain how we can find the address location of INT 0AH in Interrupt vector table. 2. What will be the content of AX register after execution of the instruction IMULCL, if CL = +1510 and AL = -13210.. 3. Suppose that DS = 1300H, SS = 1280H, BP = 15A0H and SI = 01D0H.Determine the address accessed by each of the following instructions andmention their type of addressing mode.i) MOV AX, [200H]ii) MOV AL, [BP-SI+200H]iii) ADD AL, [SI + 0100H]

I am trying to better understand memory access in computers, please answer the sample question below. Assume that the page table can held in registers of the MMU. It takes 8 ms (milliseconds)to service a page fault if there is an empty frame or if the replaced page is not altered, and20 ms if the replaced page is altered. Memory access time is 100 ns (nanoseconds). It has been empirically measured that the page to be replaced is altered 75% of the time.Obtain the maximum probability of page fault for an effective memory access time ≤ 200ns.

I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?

I ONLY NEED 3 AND 4 Suppose memory has 256KB, OS use low address 20KB, there is one program sequence: Prog1 request 80KB, prog2 request 16KB, Prog3 request 140KB Prog1 finish, Prog3 finish; Prog4 request 80KB, Prog5 request 120kb Use first match and best match to deal with this sequence (from high address when allocated) (1)Draw allocation state when prog1,2,3 are loaded into memory?  (2)Draw allocation state when prog1, 3 finish?  (3)use these two algorithms to draw the structure of free queue after prog1 , 3 finish (4) Which algorithm is suitable for this sequence ? Describe the allocation process?

What will be the contents of AX, BX, CX and DX registers after the execution of the following program?                                 MOV DX, 1234                         MOV CL, 0F                         MOV BH, AB                         MOV AX, 6589                         ADD DX, AX MOV AH, 12               Lab1: OR AH, CL MOV DL, 41 MOV BX, F0 MOV CL, 3A LOOP Lab1 INC BX SHR BX,2

Task#1: Assembly Language Programming: Write down the states of RAM and registers, in line by line Debugging Mode, in the following given scenarios. [org 0x100]mov ax, 3add ax,1mov ax,2mov bx,3sub bx,axadd ax,bxmov ax,0x4c00int 0x21 Solution: Ax = Ax = Ax = Ax = and Bx = Ax= and Bx= Ax= and Bx= Ax= and Bx= only 7 min left do fast donot copy from internet there it is wrong

1. In this exercise we examine in detail how an instruction is executed in a single cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10001100101001100000000000111000 Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R3 1 0 1 -2 4 -6 4 -10 -12 -14 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top of the following Figure) for this instruction word? b. What are the values of ALU control unit’s inputs (ALUOp and Instruction operation) for this instruction? c. For the ALU and the two add units, what are their data input values?  ALU                                       Add (PC+4)                          Add (Branch) Input#1 Input#2                Input#1 Input#2               Input#1 Input#2

Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.

Section 1.0 cites as a pitfall the utilization of a subset of the performace equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3GHz, an average CPI of 0.75, and requires the execution of 1.0E9 instructions. (1) A common fallacy is to use MIPS to compare the performace of two different processors, and consider that the processor with the largest MIPS has the largest performance. Check if this is true for P1 and P2. (2) Another common performace figure is MFLOPS, defined as   MFLOPS = No. FP operations / (execution time x 1E6)   but this figure has the same problems as MIPS. Assume that 40% of the instructions executed on both P1 and P2 are floating-point instructions. Find the MFLOPS figures for the processors.

Assume that the registers have the following values (all in hex) and that CS=1000, DS=2000, SS=3000, SI=5400, DI=2200, BX= 6000, BP-1000, SP= 1100, AX=4312, CX=11CB, and DX= 2245. Calculate the physical address of the memory where the operand is stored and the contents of the memory locations in each of the following addressing examples: 1- MOV (SI), DL. 2- MOV [DI-9), CH 3- MOV [BP], AL. 4- MOV (SI+BX]. AH. 5- MOV BX, 22AC. 6- MOV [SI]+50, BX. 7- MOV [2000]. DX. 10- MOV (SP), BH. 8- MOV BL, DH 9- MOV [BX]+10, AX.

1. Consider the following y86-64 program: .pos 0x0irmovq $128,%rdxirmovq $3,%rcxrmmovq %rcx, 0(%rdx)irmovq $10,%rbxmrmovq 0(%rdx), %rax # Load %raxaddq %rbx,%rax        # Use %raxhalt What value will be in register %rbx when the halt statement is reached? Give your result in hex, without leading 0s or 0x. Answer:   2. Consider the following y86-64 program: .pos 0x0irmovq $128,%rdxirmovq $3,%rcxrmmovq %rcx, 0(%rdx)irmovq $10,%rbxmrmovq 0(%rdx), %rax # Load %raxaddq %rbx,%rax        # Use %raxhalt Memory is written to by this program. What is the memory address? Give your result in hex, without leading 0s or 0x. Answer:   3. Consider the following y86-64 program: .pos 0x0irmovq $128,%rdxirmovq $3,%rcxrmmovq %rcx, 0(%rdx)irmovq $10,%rbxmrmovq 0(%rdx), %rax # Load %raxaddq %rbx,%rax        # Use %raxhalt Memory is written to by this program. What value is written to memory? Give your result in hex, without leading 0s or 0x. Answer: 4. Consider the following y86-64 program: .pos 0x0irmovq…

1- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex.          addi $t0, $Zero, -50          andi $t1, $t0, 7 Loop:and $t1,$t0,$t1          Sw $t0, 40 ($t1)          Bne $t1,$ zero, Loop   2- What is the MIPS assembly instruction for the following machine code?                       0x8C220004

A system is using segmentation to map physical memory. Current segment table is as follows. Some of the entries are stored in associative registers as given in second table. Assume that the register access time is 10 nanoseconds and memory access time is (10 x 7) nanoseconds;   Find the physical memory address for each of the following logical memory addresses given by <Segment no, offset> Calculate effective memory access time for each (a) <0,3700> (b) <2,3780> (c) <1,200>

The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: R-Type BEQ JMP LW SW 40% 25% 5% 25% 5% Also, assume the following branch predictor accuracies: Always - Taken Always - not - taken 2-bit 40% 60% 75% 1.1 Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used. 1.2 Repeat 1.1 for the “always-not-taken” predictor. 1.3 Repeat 1.1 for the 2-bit predictor. 1.4 With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way…

help for the mips code. dont use AI, divi is not using in mips. Q1)Suppose $t1 stores the base address of word array A and $s2 is associated with h,        convert to the following instruction into MIPS.        if A[m+3]<20:              A[m+1] = 5          else:               A[m] = 1Q2)   Assume only $s1, $s2, $a0, $v0 registers can be used. Procedure calling convention MUST be followed.   def func(x):      a = x/3      if a == 20:          return a      else:          return 1

What are contents of R5 after execution to each of the following instruction? (Assume R2 contains OxABCD01235 and R3 contains 0x1111 1111) ADD R5, R2, R3 SUB R5, R2, R3 XOR R5, R2, R3 ADD R5, R2, R3 ROR R2, # 0x8 ADD R5, R2, # 0x0F

In this exercise, we examine how data dependences aff ect execution in the basic 5-stage pipeline. Problems in this exercise refer to the following sequence of instructions:or r1,r2,r3or r2,r1,r4or r1,r1,r2Also, assume the following cycle times for each of the options related to forwarding: Without Forwarding With Full Forwarding With ALU-ALU Forwarding Only 250ps 300ps 290ps Indicate dependences and their type.Assume there is no forwarding in this pipelined processor. Indicate hazards and add nop instructions to eliminate them.Assume there is full forwarding. Indicate hazards and add NOP instructions to eliminate them.What is the total execution time of this instruction sequence without forwarding and with full forwarding? What is the speedup achieved by adding full forwarding to a pipeline that had no forwarding?Add nop instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).What is the total execution…

3- What is the difference between: a- MOV BX,[1234H] and LEA BX,[1234H] b- LDS AX,[200H] and LES AXX,[200H] 4-Use MOV to load address of memory MEM1.

Problem 4: Give a block diagram for a 8M x 32 memory using 512K x 8 memory ch book] [Hints: Figure 5.10 in the

1.BL=00, after instruction DEC BL is executed, CF =? 2.CH=80H; after ROL CH, 1; CH=?

Please solve and show all work. Thank you. Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. addi $t0, $s6, 4 add  $t1, $s6, $0 sw   $t1, 0($t0) lw   $t0, 0($t0) add  $s0, $t1, $t0

2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex.          addi $t0, $Zero, -50          andi $t1, $t0, 7 Loop:and $t1,$t0,$t1          Sw $t0, 40 ($t1)          Bne $t1,$ zero, Loop